ISCAS 2002

IEEE International Symposium

on Circuits and Systems

Sunday, 26 May 2002 - Wednesday, 29 May 2002

Scottsdale Princess Resort

Scottsdale, Arizona

ISCAS 2002 Theme: Circuits and Systems for Ubiquitous Computing


MOS Modeling as a Basis for Design Methodologies:
New Techniques for Modern Analog Design
Daniel Foty
David Binkley
Sunday May 26, 2002, 1:30 PM - 4:45 PM


Amid the blizzard of design-automation technologies, the analytical MOSFET models (and their associated model parameter sets) receive scant attention from the design community. However, these models and parameter sets are fundamental to the design process, since they represent the critical "communication link" between a design group and its wafer foundry. Particularly for analog design, there is a need for the models to be more than a “black box;” the models should provide the ability to support modern analog design methodologies.

The first part of this tutorial will examine the present "infrastructure" of MOS modeling for circuit simulation, with particular emphasis on how history has played a role at least as large as that of engineering. In recent years, the entire structure of MOS models has been evolving into continually more complicated and empirical forms, opening up a "reality gap" between a model's mathematical structure and circuit design usage. Among the many severe consequences of the present situation, the MOS models have become completely removed from good circuit design practices, particularly for analog design; many common analog circuits cannot even be simulated properly using "modern" MOS models!

The second part of this tutorial will make the connection between MOS modeling and a modern approach to designing analog and digital integrated circuits. Transistor-level analog CMOS design is greatly complicated since, at a given MOSFET drain current, there are two independent degrees of design freedom: inversion level and channel length. The methodology allows management of the tradeoffs in circuit bandwidth, transconductance, output conductance, DC gain, DC matching, linearity, white noise, flicker noise, and layout area resulting from the selection of inversion level and channel length. This permits MOSFET sizing for optimal bandwidth, optimal DC matching, balanced compromises in bandwidth and DC matching, and other combinations of circuit performance. The methodology permits operation anywhere in the continuum of MOSFET operation - weak, moderate, or strong inversion.

About the Presenters:

Daniel Foty is the Founder and President of Gilgamesh Associates in Fletcher, Vermont, an Adjunct Associate Professor of Electrical Engineering at the University of Tennessee, and the Director of Design Methodologies at Nanopower Technologies in Newport Beach, California.

David Binkley is an Associate Professor of Electrical Engineering at the University of North Carolina/Charlotte.

The 2002 IEEE International Symposium on Circuits and Systems is sponsored by:
and supported by:
Texas Instruments
Date     Announcement
    6 March     Preliminary conference schedule available. See "Program" area of website.
    29 January     Session information for accepted papers is now available.
    19 January     The list of accepted papers has been posted. Please see the Paper Submission page for the link.
Tutorial Proposal Deadline         Friday, 21 September 2001
Paper Submission Deadline         Monday, 29 October 2001
Paper Acceptance Notification         Friday, 18 January 2002
Author Registration Deadline         Friday, 1 March 2002
Final Submission Deadline         Friday, 1 March 2002
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