Signal Integrity for High-Performance Low-Power Circuits
Sunday May 26, 2002, 1:30 PM - 4:45 PM
With the advance of semiconductor manufacturing, EDA, and VLSI design
technologies, circuits with increasingly higher speed are being integrated
at an increasingly higher density. This trend causes more signal integrity
problems for both signal nets and power-ground networks.
We first discuss the signal integrity problem for signal nets.
We present the interconnect extraction and noise modeling for
both capacitive and inductive coupling, and describe
noise minimization via layout optimization, including driver sizing
and buffer insertion, wire sizing and spacing, shield insertion,
and differential signaling.
We then discuss the power-ground integrity due to IR-drop, L di/dt noise,
or LC resonance. We address its importance, verification methodology,
and problem solution. Special focus will be given to inductance related
L di/dt noise and LC resonance, which has been over-looked and will
become significant in the near future.
About the Presenters:
Dr. Lei He obtained the Ph.D. degree in computer science
from UCLA, and joined the faculty of ECE dept., University of
Wisconsin at Madison in 1999. He has done extensive research
on interconnect modeling and optimization. He was the primary
developer of UCLA TRIO package, a tool set widely used for
interconnect synthesis with routing construction, buffer insertion,
device sizing, wire sizing, and wire spacing. He worked with Cadence
in 1996 summer and verified the 2.5D capacitance extraction methodology
shipped with SE 5.0 product. He worked with HP Laboratories in 1998 to 1999
and proposed the inductance extraction methodology used in state-of-the-art
microprocessor designs. In 2000 summer, He was a consultant at Synopsys
for design closure related to timing and signal integrity.
He co-authored an embedded tutorial "Interconnect Design for
Deep Submicron ICs", ICCAD97, and was the organizer and co-speaker
for a half-day tutorial "Interconnect modeling and design for
gigascale systems-on-chip with consideration of inductance" in
the 2000 IEEE ASIC/SOC conference.
Dr. Shen Lin got his Ph.D from the EECS department of
UC, Berkeley in 1992, and is the CTO and co-founder of Apache
Design. He joined IBM T.J. Watson Research Center. from 1992-1995,
and LSI Logic from 1995- 1997. From 1997-2000, he was with HP Labs
working on design methodology, signal integrity, inductance,
power/ground optimization, and clock skew minimization.
He held one US patent on low power circuit design
technique, filed four US patent applications, and
published numerous technical papers. He is a co-author
of the whole-day tutorial on signal integrity in DAC'2000, and
is a co-speaker for an embedded tutorial in ICCAD'2001.
| 6 March
|| Preliminary conference schedule available. See "Program" area of website.
| 29 January
|| Session information for accepted papers is now available.
| 19 January
|| The list of accepted papers has been posted. Please see the Paper Submission page for the link.
|Tutorial Proposal Deadline
|| Friday, 21 September 2001
|Paper Submission Deadline
|| Monday, 29 October 2001
|Paper Acceptance Notification
|| Friday, 18 January 2002
|Author Registration Deadline
|| Friday, 1 March 2002
|Final Submission Deadline
|| Friday, 1 March 2002