VLSI Arithmetic Circuits |
| Session Type: Lecture
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| Time: Monday, May 27, 1:30 - 3:00
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| Location: Ballroom D
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| 2199: A 3.3V 1GHZ HIGH SPEED PIPELINED BOOTH MULTIPLIER |
| CHOW, Hwang-Cherng: Chang Gung University |
| WEY, I-Chyn: Chang Gung University |
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| 1560: A 1.67 GHZ 32-BIT PIPELINED CARRY-SELECT ADDER |
| Kim, Youngjoon: Kaist |
| Sung, Ki-Hyuk: Kaist |
| Kim, Lee-Sup: Kaist |
| |
| 1269: AN INTERCONNECT OPTIMIZED FLOORPLANNING OF A SCALAR PRODUCT MACROCELL |
| Gu, Jiangmin: Nanyang Technological University |
| Chang, Chip Hong: Nanyang Technological University |
| Yeo, Kiat Seng: Nanyang Technological University |
| |
| 1385: LOW DEPTH CARRY LOOKAHEAD ADDITION USING CHARGE RECYCLING THRESHOLD LOGIC |
| Celinski, Peter: Adelaide University |
| Al-Sarawi, Said: Adelaide University |
| Abbott, Derek: Adelaide University |
| Lopez, Jose F.: Universidad de Las Palmas de G.C. |
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| 1627: A ROBUST SELF-RESETTING CMOS 32-BIT PARALLEL ADDER |
| Jung, Gunok: University of Minnesota |
| Sundarajan, Venkat: University of Minnesota |
| Sobelman, Gerald: University of Minnesota |
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